This invention relates to flash memory devices and methods and apparatus for commanding and controlling flash memory devices.
Flash memory devices are solid state non-volatile memory devices that allow users to electrically program and erase information. Flash memory devices typically support both read and write cycles that respectively allow data to be read from and programmed into the flash memory. In the earliest flash memory devices, data and address buses internal to the flash memory had to be carefully controlled by a CPU or other external processor to perform even the simplest of tasks such as writing data to or reading data from a flash memory cell. As flash memory devices have matured, external processors have been relieved of this burden by incorporating state machines into the flash memory devices.
A state machine is a logical device whose current state or status is determined by its previous state or status. Each command received by a state machine determines not only what action the state machine will take (depending upon its current state), but also determines the next logical state the state machine will occupy. State machines can be implemented as hard-wired logic devices, or as microcontrollers configured to execute a state machine algorithm.
The incorporation of state machines into flash memory devices has allowed flash memory devices to autonomously perform simple tasks like programming and erasing data without external processor control. As a result, an external processor can issue a high level command to a flash memory device, and the state machine within the device can autonomously interpret the command, and perform the tasks that are necessary to execute the command. As the state machine performs these tasks, it can set bits in a status register that can be monitored by the external processor to determine the command""s execution status.
Currently, state machines incorporated into flash memory devices are hard-wired by device design to autonomously interpret predetermined write cycles as commands, and to execute hard-wired or predetermined algorithms to fulfill those commands. As a result, currently available flash memory devices are only capable of interpreting the limited number of predetermined commands that have been logically designed into their state machines. As new features requiring new commands are developed for flash memory devices, new state machines must be specifically designed and developed to interpret and execute the new commands. Developing new state machines whenever new commands are developed for flash memory devices is a time-consuming process that is both inflexible and subject to logical design errors.